1. Field of the Invention
This invention relates to a method for the manufacture of a package to encapsulate an integrated circuit device. More particularly, a chip-scale package is manufactured by flip-chip bonding input/output pads on the integrated circuit device to bond pads on a substrate. The substrate further includes at least one aperture to enable the introduction of a low viscosity dielectric between the substrate and the integrated circuit device. The bonded assembly is then encapsulated in a molding resin.
2. Description of the Related Art
One package for encapsulating integrated circuit devices such as silicon-based semiconductor dice is the flip chip package. In this package, a semiconductor die has bumped bond pads on an active surface which are soldered to a matching array of bond pads on a substrate. The semiconductor die and attached surface of the substrate are then encapsulated in a molding resin. The molding resin, typically a thermosetting epoxy, is applied at a relatively high temperature and velocity and could damage the semiconductor die or solder interconnects on impact. Typically, an underfill of a fluid epoxy is disposed between the semiconductor die and the substrate to protect the flip chip bonds and circuitry during encapsulation with the molding resin.
Typically, the underfill is dispensed along one or two sides of the die at an elevated temperature to reduce viscosity and facilitate the underfill material flowing quickly between the semiconductor die and the substrate. This method has poor control of the spread of the underfill material and it is necessary for there to be up to three millimeters of clearance between the perimeter of the semiconductor die and the edge of the substrate to accommodate the underfill flow. As a result, the length and width of the semiconductor package cannot be smaller than six millimeters plus the length and width of the semiconductor die. This is a significant increase in occupied real estate over chip scale packages where the perimeter of the package is intended to approach the perimeter of the semiconductor die. Since air pockets are typically trapped between the integrated circuit and the substrate, the method is also prone to incomplete fill and voids that impact reliability. Voids or incomplete fill could also occur due to the limited space between the semiconductor die and the substrate.
While it is known to use vacuum assisted molding, this is an expensive process and requires the use of molded compounds having a fine filler, on the order of less than 50 microns, to fill in the gap between the semiconductor die and substrate.
U.S. Pat. No. 6,573,592 to Bolken discloses a flip chip semiconductor package in which the substrate includes side walls to control the flow of underflow material. The underfill material is introduced along the perimeter of the semiconductor die.
U.S. Pat. No. 6,369,449 to Farquhar, et al. discloses a flip chip package having a substrate with contact pads and aperture. After solder bonding input/output pads to the array of contact pads, a high viscosity epoxy is flowed under pressure through the aperture to fill the space between the semiconductor die and the substrate. U.S. Pat. Nos. 6,369,449 and 6,573,592 are incorporated by reference in their entireties herein.
There remains, a need for the method of a flip-chip package having a chip scale perimeter that does not suffer from the disadvantages of the prior art.